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Smirnov, N. A. (Автор МИЭТ (студент); Смирнов Назар Александрович). Automation of architectural verification of RISC-V processor core based on the RiscoF framework / N. A. Smirnov. - Текст : электронный // МОЛОДОЙ УЧЕНЫЙ. - Казань : Молодой ученый, 2025. - № 51(602). - С. 19-21.
Авторы:	Smirnov, N. A.
Ключевые слова:	RISC-V, PROCESSOR VERIFICATION, COMPLIANCE TESTING, RISCOF, TEST AUTOMATION, INSTRUCTION SET ARCHITECTURE
Аннотация:	The article discusses the problem of high entry barriers to architectural verification of processor cores based on the open RISC-V architecture. It analyzes existing barriers that prevent the widespread use of compliance testing in educational and open-source projects. It proposes a universal verification environment architecture based on the official RiscoF framework, which automates the process of verifying the compliance of cores with the RISC-V International specification requirements. It describes the modular structure of the solution, which includes a parameterizable adapter, a library of testbench templates, and a report generation system
Поиск:	Источник